As electronic devices continue to evolve, there is a constant tension between size, speed, and power consumption. With increasing data access speed, current consumption has become a challenge in some memory designs. Especially, an amount of a current consumption on data buses such as read/write data buses (RWBS) can occupy more than 10% of total current consumption in some dynamic random access memory (DRAM) designs. For example, in some double data rate (DDR) 3 or DDR4 implementations, 128 bits of data (e.g., a burst length of 8*16 I/O data buses) are required to be transferred simultaneously. A method to lower the voltage level applied to RWBS is considered to solve this problem, however, it becomes difficult to realize both a high data access speed and lowering the voltage level applied to RWBS.